1. Field of the Invention
The invention relates generally to a flash memory cell and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell. More particularly, the invention relates to a flash memory cell having a silicon-oxide-nitride-oxide-silicon (SONOS) structure in which silicon, an oxide film, a nitride film, an oxide film and silicon are sequentially stacked, and method of manufacturing the same, and programming/erasing/reading method in the flash memory cell.
2. Description of the Prior Art
A flash memory cell is a non-volatile memory device that is electrically programmed and erased. A basic structure and programming/erasing operation of the flash memory cell will be described below.
FIG. 1 is a cross-sectional view of a conventional flash memory cell for describing the structure and programming/erasing operation of the flash memory cell.
As shown in FIG. 1, the flash memory cell includes a tunnel oxide film 12, a floating gate 13 consisting of a first polysilicon layer, an ONO dielectric film 14, a control gate 15 consisting of a second polysilicon layer, and source and drain 16a, 16b that are formed at both edges of the tunnel oxide film 12, all of which are sequentially stacked on a semiconductor substrate 11.
In the flash memory cell constructed above, if the control gate 15 is applied with a high voltage of about 9V and the drain 16b is applied with a voltage of about 5V having about 5 μs pulse, channel hot electrons generated on the surface of the semiconductor substrate 11 below the gate oxide film 12. The generated hot electrons are then stored at the floating gate 13 through the gate oxide film 12, so that a programming operation is performed.
Further, if the control gate 15 in the flash memory cell is applied with a negative voltage of about −9V and the semiconductor substrate 11 is applied with a high voltage of about 9V, the electrons stored at the floating gate 13 are discharged from the floating gate 13 based on a FN (Fwoler Nerdheim) tunneling effect, so that an erasing operation is performed.
The flash memory cell constructed above is formed by exposure/etching process several times. Therefore, there are problems that the process steps are complicated and obtaining a process margin is difficult. In addition, the conventional flash memory cell requires a large area compared to peripheral devices and only data of one bit per cell can be stored. Due to this, there is a problem that the efficiency is degraded in view of the level of integration.
Meanwhile, an edge portion of the tunnel oxide film is damaged by various etching and/or ion implantation processes for forming the control gate and the floating gate after a tunnel oxide film is thinly formed. Thus, there is a problem that the charge storage capacity of the floating gate is degraded. In this case, as a defective cell may occur in a worse case, there is a problem that reliability of the device and the process is degraded.